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Cypress Semiconductor /psoc63 /BLE /BLESS /LL_CLK_EN

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Interpret as LL_CLK_EN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLK_EN)CLK_EN 0 (CY_CORREL_EN)CY_CORREL_EN 0 (MXD_IF_OPTION)MXD_IF_OPTION 0 (SEL_RCB_CLK)SEL_RCB_CLK 0 (BLESS_RESET)BLESS_RESET 0 (DPSLP_HWRCB_EN)DPSLP_HWRCB_EN

Description

Link Layer primary clock enable

Fields

CLK_EN

Set this bit 1 to enable the clock to Link Layer.
CY_CORREL_EN

If MXD_IF option is 1, this bit needs to be set to enable configuring the correlator through BLELL.DPLL_CONFIG register
MXD_IF_OPTION

1: MXD IF option 0: CYBLERD55 correlates Access Code 0: MXD IF option 1: LL correlates Access Code
SEL_RCB_CLK

0: AHB clock (clk_sys) is used as the clock for RCB access 1: LL clock (clk_eco) is used as the clock for RCB access
BLESS_RESET

0: No Soft Reset 1: Initiate Soft Reset Setting this bit will reset entire BLESS_VER3
DPSLP_HWRCB_EN

Controls the DPSLP entry and exit writes to RD and controls the active domain reset and clock. 1 - LL HW controls the RD active domain reset and clock. 0 - The RD active domain reset and clock. Must be controlled by the FW

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data